安全验证将成为芯片签核项，欧盟CRA如何改变芯片设计与验证

Europe’s Cyber Resilience Act (CRA) will soon require chipmakers to prove their silicon is secure. The tools to produce that proof already exist, but they were built for a different purpose.

Europe goes first, again

On Sept. 11, the first operational part of the EU’s Cyber Resilience Act went live. From that day, any company selling a product with digital elements in Europe must flag actively exploited vulnerabilities and severe security incidents within 24 hours, with a fuller report within 72 hours, through a new reporting platform run by the EU’s cybersecurity agency, ENISA. The duty covers products already on the market, including ones shipped years ago. The rest of the law, the part that defines how products must be designed and assessed, applies from December 2027.

Europe is not the only one moving. Japan has set the rules for a new scheme that rates the security of companies in its supply chains, and the U.S. is set to require connected consumer devices bought by federal agencies to carry its Cyber Trust Mark label from January 2027. These are softer instruments, though: a voluntary rating, a label, a procurement rule. The CRA is binding law, with CE marking, fines, and a reporting clock, and it applies to anyone who sells into Europe, wherever they are based. As usual, the EU leads in regulation, for good and for bad.

What struck me while looking through the details is how directly the law reaches into our industry. Most of the commentary on the CRA has been written by lawyers and software security people, and it treats chips as a footnote. However, I believe that the CRA will change how chips are designed and verified, in ways the design community has barely started to discuss.

Chips are named in the law

The CRA sorts products into tiers by risk. Most products sit in a default category and can assess themselves. The law then lists specific product types in higher tiers, and chips are among them: microcontrollers and processors with security functions, tamper-resistant versions of those, and secure elements and smartcard chips at the top (the law firm CMS has a clear summary). For the top tiers, self-declaration is no longer enough, and an outside evaluator has to assess the product before it can carry the CE mark.

There is some legal nuance about whether a chip is a regulated product in its own right or is caught as a component of one, and a lot will depend on how customers use it. For a vendor of secure microcontrollers selling into Europe, though, the direction is clear.

The timing is where it gets uncomfortable. The standards that will define what compliance means in practice are still being written. According to a status update presented at a recent SEMI webinar, the first general standards, covering principles and risk management, went to a final vote at the end of September. The catalog of technical security controls, the closest thing to a list of what a product must actually do, is targeted for October 2027, about six weeks before the law applies. The chip-specific standards were already projected a year ago to arrive months after the Commission’s deadline.

For software, late rules are painful. For silicon, they are much worse than that. A chip taping out today will ship in 2028 under the CRA, and its security architecture is being frozen now, against requirements that have not been written yet. Software can be patched after the fact, but a mask cannot.

Who is in the room

SEMI’s CRA webinar was organized by its manufacturing cybersecurity consortium. The speakers were two compliance managers from ASML and a consultant, and the discussion was almost entirely about fab equipment. That makes sense, since a lithography scanner is a connected, software-heavy machine, and its maker is a CRA manufacturer like any other. The equipment makers have organized quickly. Their working group has drafted a position paper, already shared with the Commission, arguing that machines that stay in service for decades cannot be treated like consumer gadgets. It asks for at least 18 months after the standards are published and for transitional relief on older contracts, and it warns that some equipment makers may reconsider Europe as a market.

The chipmakers have organized too, in a different forum. The European committee writing the chip-specific standards is chaired by Infineon, with STMicroelectronics as secretariat, and its working groups are convened by ST, NXP, Infineon, and AMD. This is how European standardization normally works, and it makes sense that the people who know the technology best write the rules. Still, IMHO, it is worth noticing that the companies most at home in certification-heavy markets are the ones defining what certification will mean for everyone else.

The group I could not find in either room is the larger design community: EDA vendors, IP providers, and verification teams. That absence is what the rest of this piece is about.

We have seen this movie before

When ISO 26262 arrived in 2011, functional safety in automotive chips moved from an engineering virtue to a set of deliverables. Safety plans, failure analyses, and verification reports became work products that someone else would check, and a whole market of tools, IP, and services grew up around producing them. Those of us in verification remember how quickly “ASIL-ready” became a sales argument.

The CRA standards follow the same logic. In the SEMI webinar, the speaker describing the core standard stressed that conformity is shown through auditable outputs, rather than by claiming that an activity took place. Each requirement comes with defined inputs, a resulting work product, and criteria an assessor can check, and the technical catalog will require traceability from threats to security objectives to the controls that address them.

To anyone in our field, that reads like the description of a verification flow. I think the CRA will do for hardware security what ISO 26262 did for safety, turning it into a sign-off item where the evidence is the product. The difference is that this time it is law rather than a carmaker’s requirement, and it covers far more than cars.

The tools exist, built for someone else

This is the part I find most interesting. Hardware security verification is not a new field. It grew up over the past decade mostly in the U.S., funded largely through defense and the trusted microelectronics agenda, with strong academic roots in groups such as Mark Tehranipoor’s at the University of Florida. The tools were built to find hardware Trojans, side channels, and debug backdoors for government customers. The CRA now offers them a second, much larger commercial customer.

The pivot has started. Arteris completed its acquisition of the security verification company Cycuity at the start of the year, and a few months later published its view of what the CRA means for chip design. Caspia, founded by Tehranipoor, now lists the CRA alongside automotive and avionics standards among the regimes its security evidence is meant to support. Amida, led by Peter Levin, has built AI-based security analysis for defense customers for years, as a dedicated unit alongside its core data business.

AI sits at the center of all three. Tehranipoor presented a multi-agent approach to SoC security verification at an ESD Alliance webinar in September, and Caspia describes its direction as an agentic platform. Amida argues that its machine-learning approach finds threats that formal methods miss. Finding bugs is only half the job, though. Since CRA compliance is shown through documented proof, AI’s ability to generate, trace, and document that proof at scale may matter just as much.

However, AI also cuts both ways. The same models that help defenders produce evidence are making it cheaper to find vulnerabilities in the first place. The Commission itself made this point when it published its CRA guidance in July, saying that recent advances in frontier AI models with cybersecurity capabilities make swift implementation of the law more pressing. If that continues, the 24-hour reporting clock will start ticking more often, and the cost of shipping a chip with an exploitable flaw will rise with it.

There is also a different philosophy in play. The CHERI Alliance, which holds the only chip security session on the SEMICON Europa program next month, argues for changing the processor architecture so that whole classes of memory-safety bugs become impossible, instead of verifying their absence design by design. Verification fits the CRA logic of proving that you did the work, while architectural approaches fit its language of security by design. Both may win budget, and they will compete for the attention of the same design teams.

Who can afford the evidence

The question I keep coming back to is what all this means for startups. An incumbent can absorb a third-party evaluation and years of maintained documentation. A young company designing a secure microcontroller, or any chip that lands in the higher tiers, may find that compliance becomes a meaningful share of its budget, and I suspect few founders have priced it in yet.

AI-driven evidence tools could lower that barrier, and that is the optimistic case. But I have argued before that task-level AI gains tend to dissolve when the surrounding workflow stays the same, and certification is about as slow a workflow as exists. Faster evidence generation helps only if evaluators can accept that evidence at a similar pace.

Europe wants both a stronger chip industry and more secure products, and the CRA clearly serves the second goal. Whether it also serves the first will depend partly on whether the design ecosystem, meaning tools, IP, and the evaluators themselves, shows up to shape what proportionate compliance looks like for silicon. The equipment makers are already in the room, and I think the design community should be there too.

Also read:

EU Cyber Resilience Act: 3 Common Misconceptions

Securing Next-Generation Defense by Design

Will Purging Chinese Tech Cost Europe Its Digital Future?

CHIP DESIGN, CYBER RESILIENCE ACT, CYBERATTACK, CYBERSECURITY, SEMICONDUCTORS, SOC